The present invention relates to an integrated circuit having a a memory cell arrangement.
A plurality of memory cells usually forms a matrix of semiconductor memory cells. Each cell can be controlled separately via a word line and a bit line.
In particular flash memories or EEPROM cells could be used as memory cells. The designation EEPROM is an English abbreviation of “Electrically Erasable Programmable Read-Only Memory”. This is a non-volatile memory, i.e. the memory information is preserved even if the memory is not supplied with energy. The memory content may be programmed by electric pulses.
The memory cell of an EEPROM consists of a field effect transistor including a floating gate. The floating gate is a conductor portion above the source drain channel of the EEPROM cell. It is electrically insulated from its surrounding, so that charges present on the floating gate cannot flow off easily. The programming of the memory cell is performed in that charges are applied on the floating gate or removed from the floating gate.
The charge present on the floating gate generates a voltage that increases or decreases the channel between the source and the drain of the EEPROM cell, i.e. the conductivity of the source drain channel is influenced by the floating gate. For reading out the memory information, for instance, a constant voltage is applied to the bit line of the memory cell which is connected with the drain. The source of the EEPROM cell is connected with the ground. The control gate of the EEPROM cell is usually controlled with a read-out voltage. Subsequently, the current flowing from drain to source is measured. The current intensity measured is a measure of how strongly the floating gate is charged.
In the uncharged state of the floating gate, current may flow through the source drain path (the channel) of the EEPROM cell. To this end, a suitable (relatively low) voltage has to be applied to the control gate. If the floating gate is charged with electrons, the channel is closed. The negative potential of the electrons on the floating gate prevents electrons from flowing through the adjacent channel. No current flows in the bit line.
The control gate of each memory cell may, for instance, be controlled to select a particular memory cell. For reading out the particular memory cell, a voltage is usually applied to the bit lie; the source is, for instance, connected with the ground. The current flow in the bit line is, for instance, collected to determine whether the floating gate is charged or not. A charged floating gate normally prevents the current flow through the channel of the selected memory cell.
Prior to the writing of switched EEPROM cells of a memory sector, all memory cells are usually first of all deleted. A high potential difference between the control gate and the source/drain channel may, for instance, be used to cause a programming or deletion of the memory cell. Depending on the polarity of the potential difference, the electrons are removed from the floating gate or applied to the floating gate. After deletion, the individual memory cells of the memory sector can be written by the respective control gates. For controlling, the respective cells are usually selectively connected by read switches with the read line and by delete switches with the delete line.
The different switches are necessary since the delete voltages for the removal of charges from the floating gates are distinctly higher than the read voltages. Usually, the delete voltages have a magnitude of approx. 5 to 20 volts. The read voltages are usually smaller than 2 volts. The intensity of the delete voltage is, however, solely predetermined by the EEPROM cells. The voltage that is sufficient to discharge or charge the floating gate may be designated as delete voltage or programming voltage of the memory cell. Read voltage is the voltage that is sufficient or used to read out the memory content of the EEPROM cell without changing the charge on the floating gate.
As delete switches, transistors are used, whose breakthrough voltage across the source/drain channel lies above the delete voltage. Such a transistor is, as a rule, larger than a transistor with a lower breakthrough voltage. Furthermore, higher control voltages are necessary at the gate of the transistor to switch the transistor. The gate voltage of the delete transistor required for switching is, for instance, in the range of 10 volts. For controlling the delete switches, level shifters are required which convert the usually relatively low control voltage of 1 to 2 volts to the required voltage of the gate of the delete switch. The level shifter is a relatively slowly switching component, so that the delete switches cannot be controlled as quickly as the read switches. As a rule, the delete switches are consequently slower and larger vis-à-vis the read switches. The delete switches are, however, required for the higher delete voltages.
The known parallel circuit of several EEPROM cells has the advantage that the number of delete and read switches for controlling the EEPROM cells can be reduced. Thus, the size and complexity of the circuit are reduced and the costs are decreased. It is an advantage of the prior known circuit configuration that entire memory sectors first of all have to be deleted for programming the circuit. This disadvantage is, however, not a grave one if the memory arrangement is programmed very rarely.
The known EEPROM memory arrangement may, for instance, be used as read only memory in which a program for controlling a vehicle system (e.g., the motor control or the anti blocking system) is stored. Such a program is rewritten rarely, so that the large delete granularity does not carry weight. On the other hand, such a program is to be executable as quickly as possible. This is because in particular an anti blocking system is to detect and remedy the blocking of a tire as quickly as possible. Consequently, it must be possible to read out the memory cells quickly so as to be able to execute the program. The number of parallel-connected memory cells does, however, increase the capacitance of the connected line and thus the access time to the individual memory cells. The requirement of quick memory access is thus in contradiction to the desire of providing a circuit that is as small and as cost-efficient as possible.
For these and other reasons, there is a need for the present invention.